1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly to a structure and a manufacturing method of a bipolar transistor.
2. Description of the Related Arts
FIG. 1 shows a conventional transistor in which an emitter region is formed by diffusing impurities from polysilicon. This silicon bipolar transistor of a polysilicon emitter structure has an advantage of increasing current amplification factor thus occupying the mainstream of the present transistor market.
Now a conventional semiconductor device and a method of manufacturing the same will be described with reference to the attached drawings.
Also, we refer to the material (David J. Roulston, "Bipolar Semiconductor Devices", McGraw-Hill, page 343-345, 1990).
FIG. 1(a) shows a section of an example of a first conventional semiconductor device. FIGS. 1(b)-(e) show sectional views of a process of making a transistor serially in accordance with a manufacturing method called Super Self-aligned process Technology (SST) developed by Sakai et. al. of NTT Corp. In this process, in order, an emitter opening is formed, no-additive polysilicon is deposited all over a wafer, arsenic is added to polysilicon by an ion implantation method, N+ type polysilicon is provided, remaining in the region within a fixed distance from the emitter opening, being processed by means of photolithography and dry etching. Furthermore, heat-treatment is applied to diffuse arsenic from polysilicon to single crystal silicon, thereby finally producing an emitter.
A second conventional technique will be described with reference to a bipolar transistor of which an intrinsic base layer is formed by an epitaxial growth method.
Then, a second conventional semiconductor device and a method of manufacturing the same will be described referring to the material: Sato, et. al., "A self-aligned selective MBE technology for high performance bipolar transistor", International Electron Device Meeting (IEDM), 1990, pp.607-610.
FIG. 2 shows a section of an example of a second conventional semiconductor device. On P.sup.- type silicon substrate 1, there is formed N.sup.+ type buried layer 2, and further on which N.sup.- type silicon epitaxial layer 3 is provided having LOCOS oxide film 14 for device separation and N.sup.+ type collector draw out region 15 formed therein. Through the above process, a silicon base 100 is composed. Subsequently, the surface of silicon base 100 is covered with silicon oxide film 6. In silicon oxide film 6, there is provided a first opening 101 for preparing a base by exposing a part of silicon collector layer 3 which constitutes a collector region and a second opening 102 for exposing collector draw out region 15.
On silicon oxide film 6, P.sup.+ type base electrode polysilicon film 7 is selectively formed, being horizontally pushed out into first opening 101 from an edge of the opening. P type polysilicon layer 10 is formed from the under surface of this pushed out portion toward silicon collector layer 3 which constitutes the collector region.
Meanwhile, on the exposed portion of silicon collector layer 3, P type base region 9 is formed with single crystal silicon produced through a selective epitaxial growth process. This polysilicon layer 10 and P type base region 9 contact with each other.
In second opening 102, N type polysilicon layer 21 is formed contacting with collector draw out region 15. P type base region 9 with the exception of an emitter forming portion, polysilicon layers 7 and 10, are covered with silicon nitride film 8 and silicon oxide film 11, respectively. On the exposed part of P type base region 9, N type emitter region 16 is formed with single crystal silicon. Aluminum based emitter electrode 18b, base electrode 18a and collector electrode 18c contact emitter polysilicon 17, polysilicon layer 7 and polysilicon layer 8, respectively.
This second conventional technique is the same as the first conventional technique in that emitter polysilicon is processed by the photolithographic process and the etching process.
With the first and the second conventional semiconductor devices (wherein emitter polysilicon is processed by patterning) and the method of manufacturing thereof, N.sup.+ type polysilicon is deposited all over the silicon substrate as an emitter electrode, then photoresist is applied on the polysilicon layer and polysilicon patterning is performed through dry etching, thereby producing, as a result, a level difference of the thickness of emitter polysilicon layer directly above the emitter layer.
However, when a minute dimension is processed in the above case through patterning in the photolithographic process, it is more difficult compared to the case with a flat surface because of unevenness of the surface. In other words, for processing a minute dimension, although the light of a short wavelength is advantageous, at the same time it has a disadvantage of narrow margin of focus, and hence the more the unevenness of the surface increases, the more it becomes unsuitable for the case with the minute dimension.
Thus, as a method with which a level difference directly above the emitter portion is controlled to a small value, there is a method to take a structure in which emitter polysilicon exists only in the emitter opening (hereinafter this structure is called a plug structure). This method can be realized in two ways.
In the first method for forming the plug structure, the emitter polysilicon is deposited and then etched back by a dry etching method. Since this method maintains a photolithographic process for patterning emitter polysilicon, it is effective economically. However, according to this method, since polysilicon deposited on a large opening is completely removed by etching back operation, it can not check the characteristics of the emitter polysilicon.
There is a second method for forming the plug structure in which polysilicon is deposited by a selective crystal growth method and then adding arsenic to the deposited polysilicon by means of the ion implantation method to form emitter polysilicon layer. With this forming method, since polysilicon is formed only in the opening on the intrinsic base, the level difference as above is not produced in the emitter polysilicon layer. However, with this method, the emitter dimension of a transistor, as a product to be used in a circuit, is on the level of several .mu.m, whereas the emitter dimension of the diffusion check transistor which is used in the manufacturing stage for checking characteristics is required to be approximately 100 .mu.m square, and characteristics of both transistors do not always coincide with each other. The reason is that when the emitter dimension becomes large, in the inside of the minute opening, arsenic to be supplied by ion implantation is not sufficiently added to the bottom part of polysilicon, resulting in that the diffusion state of emitter impurities (here: arsenic) varies depending upon the size of the opening.
Current high performance bipolar transistors have a base junction depth X.sub.JB and an emitter junction depth X.sub.JE which are made very shallow for realizing high speed characteristics of the transistor. For example, according to IEEE International Electron Devices Meeting (IEDM), 1989, pp.221-224, the base depth is reported as 0.09 .mu.m. As a normal method for forming the emitter, the emitter region is formed by making N type impurities such as arsenic or phosphorus diffuse from the surface of the emitter polysilicon into the single crystal base region by applying heat-treatment to the emitter polysilicon (hereinafter called as "emitter push in"). This diffusion is largely influenced by the condition of the interface between the single crystal base and the emitter polysilicon. In other words, prior to deposition of polysilicon, a natural oxide film of approximately 10 angstrom in thickness resides on the surface of the single crystal base. This natural oxide film has dispersed thickness per wafer and poor thickness uniformity in the same wafer. Therefore, the emitter push in process is applied, such that, a piece of transistor is processed by emitter push in operation as a trial and its characteristics are measured (hereinafter a transistor to be measured is called "diffusion check transistor"), and according to the measurement result, the remaining wafers in the same lot are processed by the emitter push in operation.
However, if a emitter is formed in the region of a size in which probing can be made (for example, 80 .mu.m.sup.2 or more) according to the above described conventional method for selectively forming emitter polysilicon, measurement can be made in that region for monitoring the emitter push in state. But, the emitter dimension of transistors which are actually used as products in the circuit is 1 .mu.m or less, whereas the emitter dimension of the transistor to be monitored is several tens .mu.m, and hence diffusion states of emitter impurities are different from each other. Therefore, it is difficult to estimate data of the transistor which is used in the actual circuit by measuring the diffusion check transistor. The reason for the difference in characteristics of both transistors is unknown, but it is thought that the diffusion depth becomes different because of the different occurrence state of the stress which may be caused by the difference between the thermal expansion coefficients of the insulation film surrounding emitter polysilicon (for example, silicon nitride film or silicon oxide film) and polysilicon.
Accordingly, it is necessary to check the diffusion condition of the transistor which has an emitter of the same size as that of the transistor to be used in the circuit. However, in this case, another problem occurs as follows.
That is, it is impossible to measure transistor characteristics on the way of a process flow.
The reason of that is, with a transistor for the conventional structure, without applying patterning to emitter polysilicon according to a combination of a photolithographic process and a dry etching method, it is impossible to form an electrode pad of a dimension which can be probed (for example, 100 .mu.m.sup.2 or more) from the emitter of the transistor having a minute (a dimension of about 1 .mu.m) emitter.